The PCI Express 3.1Architecture

PCI EXPRESS 3.1 ARCHITECTURE

INTRODUCTION

The PCI Express System Architecture course starts with a high-level view of design to provide the big-picture context and then drills down into the details for each part of the design, providing a thorough understanding of the hardware and software protocols.

This course describes additional features added to the architecture when moving from PCIe specification revision 1.1 to 2.0 to 2.1 to 3.0 and 3.1.

 

TRAINING OUTLINE

1.    PCI Architecture Background Foundation

  •  PCI Legacy Configuration Transaction Generation

 

2.    PCI Express Features and Architecture Overview

  • Layered Architecture
  • TLP, DLLP, and Ordered Set Packet Format Overview
  • Protocol Overview

 

3.    Configuration Overview

  • Legacy and Enhance Configuration Transaction Generation
  • Header 0/1, Capability, and Extended Capability Register Overview
  • Bus Enumeration
  • Arbor Lab: Scan Your System and Determine Topology

 

4.    Address Space and Transaction Routing

  • Switch Routing Mechanism
  • Arbor Lab: Debug Problem with Plug-and-Play Address Mapping

 

5.    TLP Format Details

 

6.    Quality of Service and Arbitration

  • TC/VC Mapping and VC/Port Arbitration

 

7.    Flow Control

  • Flow Control Initialization
  • Runtime Flow Control Update Mechanism

 

8.    Transaction Ordering

  • Simplified Ordering Table (2.1)
  • ID-Based Ordering (2.1)

 

9.    DLLP Format Details

 

10.         ACK/NAK Protocol

  • Error Recovery Mechanism
  • Examples of Variety of Error Scenarios
  • Nullified Packets and Store-and Forward vs Cut-Through Mode

 

11.         Physical Layer Logic (Gen1/Gen2)

  • Byte Striping/Unstriping
  • Scrambling/Unscambling
  • 8b/10b Encoding/Decoding
  • Serializing/Deserializing

 

12.         Physical Layer Logic (Gen3)

  • 128b/130b Encoding/Decoding

 

13.         Physical Layer Electrical (Gen1/Gen2/Gen3)

  • Differences Between Generations
  • De-Emphasis
  • Gen3 Equalization

 

14.         Link Initialization and Link Training

  • Detect, Polling, Configuration, L0, Recovery (Retraining) States
  • Power Management States: L0, L0s, L1, L1 Active, L2, L3 Power States
  • Gen3 Equalization Training
  • Link Width and Speed Changing

 

15.         Error Detection and Handling

  • Correctable, Non-Fatal and Fatal Errors
  • Arbor Lab: Determine Source and Error Reporting Mechanism

 

16.         Power Management

  • Software-Controlled Power Management
  • Active Hardware-based Power Management
  • Optimized Buffer Flush Fill (OBFF) (2.1), Latency Tolerance Reporting (2.1), and L1 Sub-States (3.1)

 

17.         Interrupt Support

  • Legacy Interrupt Handling
  • MSI Interrupt
  • MSI-X Interrupt
  • Arbor Lab: Investigate Source of MSI Interrupt and Delivery

 

18.         System Resets

  • Fundamental Reset (Cold and Warm Reset) and In-band Reset (Hot Reset)
  • Function Level Reset (FLR)

 

19.         Hot Plug and Power Budgeting

  • Hot Plug Controller
  • Dynamic Power Allocation (2.1)

 

20.         2.1 and 3.1 ECN

  • Internal Error Reporting
  • Multi-Casting
  • Atomic Operations
  • Resizable BARs
  • Alternative Routing-ID Interpretation
  • Extended Tag Enable
  • TLP Processing Hints
  • Downstream Port Containment
  • Lightweight Notification
  • Process Address Space ID
  • Precision Time Measurement
  • Protocol Multiplexing
  • Address Translation Services

 

WHO SHOULD ATTEND

This course is hardware-oriented but is suitable for both hardware and software engineers. This course is ideal for RTL Design Engineers, Chip Design Engineers, System Design Engineers, or System Board-Level Design Engineers who need a broad understanding of PCI Express. This course is also suitable for chip-level and board-level Validation Engineers.

 

DURATION

5 Days (9.00 am – 5.00 pm)

 

TRAINING DATE(S) & VENUE

25 – 29 September 2017 @ PSDC, Penang

 

COURSE FEE

RM7,250/participant (excluding  6% GST). Course fees are HRDF claimable.

 

TRAINER

MR RAVI BUDRUK

VICE PRESIDENT, MINDSHARE

Mr Ravi Budruk is Vice President at MindShare, a technology training company. He has over 20 years of industry experience.

Prior to joining MindShare, Mr Budruk was an Intel processor-based Chipset Design Engineer, System Architect, and Manager at VLSI Technology, Inc. Mr Budruk has trained thousands of hardware and software engineers in various subjects of computer architecture. Mr Budruk is an industry expert on topics such as Intel x86 Processor Architecture, bus architectures such as Intel QuickPath Interconnect, HyperTransport, PCI Express.PCI/PCI-X, IEEE 1394, ISA, PC System architecture, and a variety of memory (DDRx) technologies. He is an excellent presenter and a dynamic speaker who brings industry-acquired experience to the class.

Mr Budruk has a Master’s of Science degree in Electrical Engineering from Purdue University and a Bachelor of Science degree (Magna cum Laude) in Electrical Engineering from Texas Tech University. Ravi Budruk is also the author of the ‘PCI Express System Architecture’ textbook. As Vice President at MindShare, he manages the business.

 

COURSE BROCHURE

Click here to download the full brochure.

 

ENQUIRIES

For further information, please contact:              

Elly Leong (ext 523/ellyleong@psdc.org.my)

Yuki Lee (ext 517/yukilee@psdc.org.my)