IO Testing, DFT, and Design Verification Fundamentals

About This Course

This course provides a better understanding of IO testing and IO DV(Design Verification) in ATE environment.

It explains in depth concepts, terminology, information on how to develop and implement tests for opens and shorts, IO pin leakage, ISB, input voltage and output voltage tests. It also provides IO DV definitions of commonly used parameters related to I/O signal pins and how these parameters are characterized in an ATE environment.

Learning Objectives

Successful students will be able to:

  • Understand I/O tests in High-Volume Testing
  • Understand why I/O Design Verification (DV) is required and how to perform basic I/O DV on a tester



Target Audience

A Product or Test Engineer with more than a year's experience or relevant exposure (e.g debug engineer, failure analysis engineer, production engineer, etc.)

Training Outline

  1. IO Testing : Introduction

  2. Fundamentals of DC Parametric Tests

  3. Design for Test (DFT) Overview of JTAG Archit

  4. Boundary Scan in IO Tests

  5. Communication Protocol : SPI BUS Overview

  6. Communication Protocol : I2C BUS Overview

  7. Importance of I/O Design Validation

  8. Basic of I/O DV Parameter