This three-day course is an intensive course aimed at providing designers/engineers with the in-depth knowledge of Verilog RTL coding from a design perspective. It introduces the participants to design flow, different RTL coding styles, things to look-out-for during RTL coding for design, as well as BKMs (best known methods) to ensure for efficient RTL coding from design perspective. The content of this course is combined with many labs to provide hands-on experience to enhance the efficiency of the course.

Upon completion of this course, participants will be able to:

  • Understand Verilog design flow
  • Understand Verilog RTL coding for IC design
  • Gain knowledge of different styles of RTL coding
  • Understand the BKMs on coding methods for efficient design
  • Know the things to look-out-for during RTL coding for design

Target Audience

Basic design knowledge is preferred but not necessary. This course is targeted for Designers, Test Engineers, Programmers, and System Architects working on ASIC, FPGA and SOC.