This is an intensive three-day course that introduces the participants to timing analysis using static timing analysis methods. The course begins with basic timing calculations and analysis on simple gate level circuits. Set-up time and hold time requirements and how it affects IC design are explained in detail. Digital circuits which cannot meet the timing requirement are shown different tweaks that can be used for timing optimization. Static timing analysis on different corners and different requirements are shown and explained in detail to the attendees. Design flow involving static timing analysis are also discussed and shown how it’s tightly integrated into the back-annotation flow prior to tapeout. This course is lab-intensive to provide participants with more hands-on experience.

Upon completion of this course, participants will be able to:

  • Understand timing analysis concepts
  • Understand requirements for setup and hold and how it affects digital circuits
  • Optimize digital circuits for timing optimization
  • Understand static timing analysis and how its incorporated into a design flow
  • Understand importance of static timing analysis on back annotation

Target Audience

Participants need to have basic design knowledge. This course is targeted for IC Designers, System Designers, Test Engineers, and System Architects working on IC design.


Participants who have attended the Basic Analog IC Design course are preferred