Intermediate Verilog Coding is aimed at existing Verilog designers. This course emphasizes on different Verilog techniques for advanced RTL coding. This course cover design issues including effective coding styles, achieving RTL code with good optimization, state machine coding techniques, ways to avoid CDC issues, and general view of behavioral modeling and test benching.

  • Write efficient RTL code
  • Understand the advantages of coding style
  • Understand complex design issues such as glitches, clock domain crossing, state machine coding, and race conditions
  • Know good coding style to achieve optimization
  • Write efficient verification testbench
  • Use different coding techniques (state machine, CDC implementation, testbench) to implement design of a Serial Peripheral Interface

Target Audience

This course is ideally suited to those who have taken the Introduction to Verilog course.


Attendees need to have basic Verilog knowledge