Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today’s microprocessor chips have one thousand times the processing power of those a decade ago. These challenges have been accomplished because of the integrated circuit industry’s ability to track something known as Moore’s Law. Moore’s Law states that an integrated circuit’s processing power will double every two years. This has been accomplished by making devices smaller and smaller. The industry is also pushing to use semiconductor devices in an increasing array of applications. To accomplish this, the industry is also driving prices down. This has created a number of challenges related to the packaging of these components.
IC Packaging Design and Modeling is a 2-day program that offers detailed instruction on the design and modeling of semiconductor packages, with special emphasis on package interactions with the die. This program is a must for every manager, engineer, and technician working in semiconductor packaging, using semiconductor components in high performance applications or non-standard packaging configurations, or supplying packaging tools to the industry. By focusing on the fundamentals of packaging design and modeling, participants will learn why advances in the industry are occurring along certain lines and not others. The key focus will be on semiconductor packaging without delving heavily into the complex physics and materials science that normally accompany this discipline.
This skill-building program is divided into four segments:
- Packaging Design Overview: Participants will learn the fundamentals of packaging design and why modeling has become critical to semiconductor packaging for today’s designs
- Mechanical Simulations: Participants will learn the fundamentals of displacement, strain, stress, energy, and how to leverage St. Venant’s Principle and apply fracture mechanics to a problem
- Thermal Simulations: Participants will learn heat transfer modeling, steady-state and transient thermal modeling, as well as industry standard and compact thermal models
- Modeling Semiconductor Packages: Participants will learn about the software used for modeling a variety of aspects of semiconductor packaging
The program offers a wide variety of sample modeling problems for participants work in class to help them gain knowledge of the fundamentals of packaging modeling. Upon completion of the program, participants will be able to identify basic and advanced principles for mechanical stress and thermal diffusion and understand how package reliability, power consumption, and device performance are interrelated. Participants will also be able to make decisions about how to construct and evaluate new packaging designs and technologies and will be introduced to wafer-level simulations, which are increasingly necessary with the advent of low-k dielectrics
Process, Product, NPI, R&D, Development, Failure Analysts, Yield, and Reliability Analysis Engineers, Researchers, Developers, and Vendors of Wafer Fab Equipment