This three-day course introduces the participants to Verilog Hardware Description Language and its usage for behavioral, structural, and RTL coding. The content of this course is combined with many labs to provide hands-on experience to enhance the efficiency of the course. The course begins with basic design flow that uses Verilog to usage of the Verilog language for design.

Upon completion of this course, participants will be able to:

  • Understand Verilog design flow
  • Gain basic understanding of Verilog coding
  • Write Verilog RTL coding
  • Write behavioral Verilog coding
  • Write testbenches to verify Verilog designs

Target Audience

Basic design knowledge is preferred but not necessary. This course is targeted for Designers, Test Engineers, Programmers, and System Architects working on ASIC, FPGA and SOC.


Participants who have attended the Basic Analog IC Design course are preferred